1. Field of the Invention
The present invention relates to circuits for generating a reset signal for a digital system upon application of power to such system. Additionally, the present invention relates to circuits for detecting low voltage condition of a power supply and to provide a signal when such low voltage condition occurs. In particular, the present invention is intended for use with custom designed logic circuits utilizing complementary symmetry metal oxide semiconductor technology (CMOS).
2. Prior Art
Means for generating a reset signal in prior art have often been in the form of circuits external to the chip or substrate on which the digital system requiring the reset signal was fabricated. For cost effective design of CMOS chips it is desirable to limit the numbers of leads or pins for external connections to as few as possible. It is, therefore, desirable to incorporate the circuit for generating the initial reset signal on the chip or substrate on which the digital systems are fabricated.
In other designs, where the circuit for generating a reset signal upon application of power was incorporated as part of the integrated circuit design, the reliability of the circuits left something to be desired because the power reset latch in many cases was assuming a wrong initial state.
In addition to the generation of a reset signal, the circuit according to the present invention provides low voltage detection. In the prior art substantial difficulty was encountered in attempts to provide reliable low voltage detection means which was not affected substantially by temperature variations. Primarily the difficulty with the prior art designs was that the signal indicative of the power supply voltage level was applied to the drain of a CMOS device and as a result was drawing large current. In the present invention the input is applied to the gate, thus avoiding influence of the wide current fluctuations with changes in temperature.